While a variety of materials configurations exist in integrate circuit structures, a common element for many integrated circuit structures is the dielectric-filled isolation trench. Isolation trenches are widely used to allow the compact arrangement of electrically active components making up the integrated circuit(s) without adverse effects on electrical operability.
When isolation trench structures are formed in a substrate (e.g., by etching), variation in trench depth often occurs between the various trenches formed on the same substrate level on different parts of the wafer. Typically, the variation may be on the order of about 10% of the intended trench depth. To ensure that all the trenches (across the entire wafer) are completely filled with dielectric isolation material, it is typically necessary to deposit sufficient dielectric material to account for the non-uniformity of trench depth.
The necessity to account for variation in trench depth results in an overfill of the shallower trenches and a fairly thick deposit over the wafer surface. Additionally, the dielectric material (typically an oxide) deposited to fill the trenches is typically conformal to some extent. Thus, the local step topography (step height) of the trenches is reflected at least to some extent in the upper surface of the dielectric deposited to fill the trenches. Large step height is normally encountered in combination with a high xe2x80x9cwithinxe2x80x9d wafer (overfill) thickness. The deeper (or higher aspect ratio) the trench to be filled, the greater the step height in the dielectric filling layer and the more overfill is required to ensure complete filling of the trench structures across the wafer.
Another use of dielectric oxides, such as silicon oxides formed by reacting tetraethylorthosilicate (TEOS) and oxygen or ozone, is for so-called interlevel dielectric (ILD), e.g., between metal interconnects of aluminum/copper or tungsten typically for back end of the line (BEOL) wiring. A general discussion of interlevel dielectrics can be found in xe2x80x9cFundamentals of Semiconductor Processing Technologyxe2x80x9d by El-Kareh, Kluwer Academic Publishers, (1995), pages 565-571, which discussion is incorporated herein by reference. Silicon oxide layers and other insulators obtained by other processes may also be used as interlevel dielectrics. For example, other widely used materials for such purposes are boron and/or phosphorous doped silicate glasses.
Chemical-mechanical polishing (CMP) to remove dielectric materials has been widely used to improve the quality and manufacturability of integrated circuit device structures. Generally, the objective in polishing is to remove the deposited dielectric material across the wafer so it remains only within the trenches (or between conductive features, e.g., metal lines) and presents a planar surface for subsequent processing.
Often, a reactive ion etching process (to reduce step height and/or overall thickness in the deposited dielectric material) is required in combination with a conventional slurry chemical-mechanical polishing (CMP) process in order to obtain proper planarization. Reactive ion etch processes are not desirable from the point of cost and/or process control.
Conventional fixed-abrasive CMP (alkaline mediumxe2x80x94pH=10.5-12xe2x80x94using a fixed-abrasive) is generally selective to step height (i.e., capable of reducing step height differential), but where the overfill is substantial, fixed-abrasive CMP is not capable of performing the necessary material removal which results in a non-planar final surface. This deficiency limits use of fixed-abrasive CMP processes to structures with small (e.g., less than 200 xc3x85) variation in trench depth or oxide overfill.
Recent improvements to fixed abrasive CMP processes disclosed in U.S. patent applications Ser. No. 09/469,922, filed Dec. 22, 1999, now U.S. Pat No. 6,294,470 and 09/702,311, filed Oct. 31, 2000, have improved the ability to planarize structures with more substantial topography, however, once topography removal has been achieved, the reduction of the planarized layer thickness (e.g., to reach an underlying etch stop layer) can become a very slow process. This problem is especially apparent for highly overfilled structures.
It would be undesirable to perform the topography reduction and thickness reduction in separate tools. Thus, there is a need for improved fixed abrasive polishing processes which are capable of more rapidly reducing the thickness of subtantially planarized oxide layers to produce a substantially planar surface while avoiding the need for RIE etch back processing or other undesirable alternatives.
The invention provides fixed-abrasive chemical-mechanical polishing processes which are effective in reducing the thickness of oxide layers, especially siliceous oxides, and more especially substantially planar oxide layers. The invention also provides fixed-abrasive chemical-mechanical polishing processes which are capable of planarizing oxide materials with even where the starting oxide layer has significant topographical variation and significant overfill. The processes of the invention are preferably characterized by a step involving simultaneous use of a fixed-abrasive polishing element and an aqueous liquid medium containing an abrasive for at least a portion of the polishing process involving reduction in thickness of an oxide layer on the substrate.
In one aspect, the invention encompasses method of reducing thickness of an oxide layer on a substrate by fixed-abrasive chemical-mechanical polishing, the method comprising:
a) providing a substrate having an oxide layer on a first surface,
b) providing an aqueous liquid medium containing a first abrasive component,
c) contacting the oxide layer of the substrate with the aqueous liquid medium and with a polishing member, the polishing member containing a fixed-abrasive component therein, and
d) maintaining the contact of step c) while providing movement between the substrate and polishing member, whereby the oxide layer becomes reduced in thickness.
The oxide layer to be polished in step a) is preferably substantially planar. The oxide is preferably a dielectric material, more preferably silica or boron phosphosilicate glass (BPSG). Preferably, step d) is conducted until an underlayer is revealed to a desired extent.
In another aspect, the invention encompasses a method of polishing an oxide layer on a substrate by fixed-abrasive chemical-mechanical polishing, the method comprising:
a) providing a substrate having an oxide layer on a first surface, the oxide layer having (i) an overfill thickness across substantially all of the layer, and (ii) portions above the overfill thickness which have a height differential relative to each other, the thickness and height being measured from a reference plane parallel with a principal plane of the substrate,
b) providing a first aqueous liquid medium containing a polyelectrolyte,
c) contacting the oxide layer with the first aqueous liquid medium and with a polishing member, the polishing member containing a fixed-abrasive component therein,
d) maintaining the contact of step c) while providing movement between the substrate and polishing member, whereby the height differential becomes reduced,
e) providing a second aqueous liquid medium containing a first abrasive component,
f) contacting the oxide layer from step d) with the second aqueous liquid medium and with the polishing member, and
g) maintaining the contact of step f) while providing movement between the substrate and polishing member, whereby the overfill thickness is reduced.
Preferably, the first aqueous medium is substantially abrasive-free. If desired, the height differential reduction steps could be replaced with an alternative method for reducing height differential.
These and other aspects of the invention are described in further detail below.